1. Field of the Invention
The present invention relates to the field of analog-to-digital converters and, more particularly, to a charge integration algorithmic analog-to-digital converter and its converting method.
2. Description of Related Art
Currently, the analog-to-digital converter (A/D converter) is in widely spread use. One of the applications is for converting the analog image signal, captured by an image sensor, into digital data for being processed by a digital signal processor. In general, such an A/D converter determines the digital value from an analog signal via a cyclic operation. Therefore, it is necessary to have an operational amplifier to sample and hold the input signal, and another operational amplifier to perform the cyclic operation. As a result, there are two operational amplifiers required. Therefore, the integrated circuit layout area is large and the miniaturization of the A/D converter is difficult.
In the known patents, U.S. Pat. No. 5,929,800, entitled xe2x80x9cCharge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifierxe2x80x9d, employs a single (or double) charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. Such an A/D converter is provided with a correlated double sampling (CDS) function, but no programmable gain amplifier (PGA) function available.
U.S. Pat. No. 5,880,691, entitled xe2x80x9cCapacitively coupled successive approximation ultra low power analog-to-digital converterxe2x80x9d, uses a capacitively coupled multiplying digital-to-analog converter (CCMDAC) to generate a succession of voltages which are compared to the input voltage to be digitized. Similar to the aforementioned patent, this A/D converter is provided with a CDS function, but no PGA function available.
U.S. Pat. No. 5,920,274, entitled xe2x80x9cImage sensor employing non-uniform A/D conversionxe2x80x9d, has A/D converters coupled to column bit lines of a sensor array. It""s A/D converting circuit is implemented by a single slope A/D converter or a non-linear successive approximation A/D converter, so as to provide a higher resolution for darker light levels while having a slower converting speed. In addition, its A/D converter is provided with a CDS function, but no PGA function available.
U.S. Pat. No. 5,886,659, entitled xe2x80x9cOn-focal-plane analog-to-digital conversion for current-mode imaging devicesxe2x80x9d, discloses a current-mode A/D converter that includes one first-order sigma-delta modulator based on a current copier cell with a constant bias that is independent of the input signals. Two or more of the first-order sigma-delta modulators may be cascaded to form a second-order or multiple-order incremental sigma-delta A/D converter to achieve high precision and high resolution analog-to-digital conversion. Such an A/D converter is provided with a CDS function, but no PGA function available.
U.S. Pat. No. 5,801,657, entitled xe2x80x9cController to maintain a certain set of environmental parameters in an environmentxe2x80x9d, describes a method for simultaneously performing bit serial analog-to-digital conversion for image sensor, which employs a one-bit comparator per channel (or set of multiplexed channels) and an N-bit digital-to-analog converter to achieve N-bit precision. Furthermore, a non-uniform quantization where the subintervals have different lengths is used to perform gamma correction or compression. The present analog-to-digital conversion is not provided with the CDS and PGA functions.
Therefore, it is known that most of the conventional A/D converters do not have both PGA and CDS functions, and moreover, the circuit layout area is large. Accordingly, there is need for the above analog-to-digital converters to be improved.
The object of the present invention is to provide a charge integration algorithmic analog-to-digital converter and its converting method for effectively reducing the circuit layout area, providing satisfactory operating speed and low power consumption, and supporting PGA, CDS and gamma correction functions.
According to one aspect, the present invention which achieves the object relates to a charge integration algorithmic analog-to-digital converter for performing an analog to digital conversion to a signal voltage and a reset voltage by referencing a top reference, a bottom reference and a middle reference. The converter comprises an operational amplifier, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. In a correlated double sampling phase, the signal voltage is sampled and charged to the first capacitor, and then the reset voltage is sampled and the charge of the first capacitor is transferred to the second capacitor, so as to determine an output voltage and an output bit, based on the reset voltage, the signal voltage, and the top reference, by the operational amplifier using a ratio of the first capacitor to the second capacitor as a gain. The output voltage is held in the third and fourth capacitors. In a first operating cycle, the third capacitor is charged to the fourth capacitor whose charge is further transferred to the output voltage, so as to determine an output voltage and an output bit, based on the previous output voltage, middle reference, top reference and bottom reference, by the operational amplifier using a ratio of the third capacitor to the fourth capacitor as a gain. The output voltage is held in the first and second capacitors. In a second operating cycle, the first capacitor is charged to the second capacitor whose charge is further transferred to the output voltage, so as to determine an output voltage and an output bit, based on the previous output voltage, middle reference, top reference and bottom reference, by the operational amplifier using a ratio of the first capacitor to the second capacitor as a gain. The output voltage is held in the third and fourth capacitors. The first and second operating cycles are alternately and cyclically executed.
According to one aspect, the present invention which achieves the object relates to a charge integration algorithmic analog-to-digital converting method for converting input voltage into digital data. The method comprises the steps of: (A) comparing the input voltage VX with a middle reference VCMB, so as to execute step (B) when VX greater than VCMB, or execute step (C) when VX less than VCMB; (B) determining VX=2*VXxe2x88x92VRT and producing an output bit of 1, and then executing step (A) again, where VRT is a top reference; and (C) determining VX=2*VXxe2x88x92VRB and producing an output bit of 0, and then executing step (A) again, where VRB is a bottom reference.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.